Modern semiconductor fabrication involves numerous steps including photolithography, material deposition, and etching to form a plurality of individual semiconductor devices or integrated circuit chips (dice) on a single semiconductor silicon wafer. Typical semiconductor wafers produced today may be at least about 6 inches or more in diameter, with a 12 inch diameter wafer being one common size. Some of the individual chips formed on the wafer, however, may have defects due to variances and problems that may arise during the intricate semiconductor fabrication process. Prior to wafer dicing wherein the individual integrated circuit chips (dies) are separated from the semiconductor wafer, electrical performance and reliability tests are performed on a plurality of chips simultaneously by energizing them for a predetermined period of time (i.e., wafer level burn-in testing). These tests may typically include LVS (layout versus schematic) verification, IDDq testing, etc. The resulting electrical signals generated from each chip or DUT (device under test) are captured and analyzed by automatic test equipment (ATE) having test circuitry to determine if a chip has a defect.
To facilitate wafer level burn-in testing and electrical signal capture from numerous chips on the wafer at the same time, DUT boards or probe cards as they are commonly known in the art are used. Probe cards are essentially printed circuit boards (PCBs) that contain a plurality of metallic electrical probes that mate with a plurality of corresponding electrical contacts or terminal formed on the wafer for the semiconductor chips. Each chip or die has a plurality of contacts or terminals itself which must each be accessed for testing. A typical wafer level test will therefore require that electrical connection be made between well over 1,000 chip contacts or terminals and the ATE test circuitry. Accordingly, precisely aligning the multitude of probe card contacts with chip contacts on the wafer and forming sound electrical connections is important for conducting accurate wafer level testing. Probe cards are typically mounted in the ATE and serve as an interface between the chips or DUTs and the test head of the ATE.
As semiconductor fabrication technology advances continue to be implemented, the spacing between electrical test contact pads (i.e. “pitch”) of dies or chips on the semiconductor wafer continues to shrink. As shown in FIG. 1, illustrating one exemplary next generation semiconductor die or DUT configuration as may be found on a wafer, testing pad pitches of 50 microns or less are desirable. The DUT testing pad pitch may be larger than the pitch between TSV (through silicon via) pads on the DUT, which may be for example 17 microns in some possible embodiments. However, a technology bottleneck occurs with existing known testing probe card designs that do not support such small testing pad pitches.
Known probe cards include a multi-layer interconnect substrate or space transformers disposed between the testing printed circuit board (PCB) and probes (such as fingers, needles, etc.) that engage the testing pads on the DUTs. The space transformers convey electrical test and power signals between the PCB and probes. Space transformers typically have a ball grid array (BGA) interconnect system on one side that mates with contacts on the testing PCB and a C4 (controlled collapse chip connection) interconnect system that mates with the upper portions of the testing probes. However, the minimum C4 pad pitch of these known space transformers is typically about 150 microns, making them incompatible with the desired 50 micron or less C4 pad pitch spacing needed to support the finer pitch probe spacing.
Accordingly, an improved testing probe card space transformer with finer C4 pad pitches is desired.